技术特性

• Performs clock and data recovery for selectable data of 622.08 Mbps (STS-12/STM-4) or 155.52 Mbps (STS-3/STM-1) NRZ data
• Meets Telcordia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, and GR-253 CORE, GR-253 ILR SONET Jitter specifications
• Lock output pin monitors data run length and frequency drift from reference clock
• Data is resampled at the output
• Active High Signal Detect (SIGD) LVPECL input
• Low jitter, high-speed outputs support LVPECL and low-power LVDS termination
• 19.44 MHz reference frequency LVTTL input
• Low power: 215 mW typical
• 3.3V power supply
• 20-pin TSSOP package
• Requires one external capacitor
• PLL bypass operation facilitates board debug process
• ESD greater than 2kV on all pins
• Pb-Free, RoHS Compliant Versions Offered

订购信息 Ordering Information

技术指标

应用领域 APPLICATION

• SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Cross Connect Equipment
• ATM and Multi-Service Switches, Routers and Switch/Routers
• DSLAMS
• SONET/SDH Test Equipment
• DWDM Termination Equipment

功能框图 Functional Block Diagram