The IP 108A is a highly integrated octal PHY transceiver for 10Base-T, 100Base-TX and 100Base-FX Fast Ethernet applications. This device is implemented with advanced 0.18um CMOS process technology for low power consumption. For the high port count switch design such as 16 or 24 or 32-port, the IP 108A can simplify the system design and ensure the targeted performance..
IP 108A can be programmed to operate in various modes through either hardware (hardware strapping pin) or software control (registers setting via SMI). It also supports SS-SMII interface to MAC controller to reduce the pin- count.
The IP 108A contains eight independent 10/ 100M PHY Transceiver and includes encoder, decoder, line driver, ADC, DAC, DSP and PLL circuits for each port. The IP 108A enters the Automatic Power Saving Mode to lower the power consumption once the link partner is disconnected. The IP 108A just needs an external OSC or crystal as the clock source, simplifying the system design. Besides the features described above, the driving capability of IP 108A can be trimmed to minimize the EMI effect by the advanced slew rate control technology