The PCKV857 is a high-performance, low-skew, low-jitter zero delay buffer designed for 2.5 V VDD and 2.5 V AVDD operation and differential data input and output levels.
The PCKV857 is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (FBOUT, FBOUT) . The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to high impedance state (3-State), and the PLL is shut down (low power mode). The device also enters the low power mode when the input frequency falls below 20 MHz. An input frequency detection circuit will detect the low frequency condition and after applying a > 20 MHz input signal, the detection circuit turns on the PLL again and enables the outputs.
When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PCKV857 is also able to track spread spectrum clocking for reduced EMI.
The PCKV857 is characterized for operation from 0 to +70 Cel
产品特点 Features
|
产品实物图![]() |
型号 | 可订购的器件编号 | 订购码 (12NC) | 产品状态 | 封装 |
PCKV857DGG | 9352 764 93118 | 量产 | TSSOP48 (SOT362-1) |
型号 | 订购码 (12NC) | 可订购的器件编号 | 化学成分 |
PCKV857DGG | 9352 764 93118 | PCKV857DGG |
档案名称 | 标题 | 类型 | 格式 |
PCKV857DGG | 70-190 MHz differential 1:10 clock driver | Data sheet | |
75017403 | NXP AISG Transceivers ASC3011, ASC3012: AISG transceivers with tunable dynamic range and multiple carriers | Leaflet |