PTN3381BBS Enhanced performance HDMI/DVI level shifter with voltage regulator, dongle detect support and active DDC buffer

The PTN3381B is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals, up to 1.65 Gbit/s per lane. Each of these lanes provides a level-shifting differential buffer to translate from low-swing AC-coupled differential signaling on the source side, to TMDS-type DC-coupled differential current-mode signaling terminated into 50 Ω to 3.3 V on the sink side. Additionally, the PTN3381B provides a single-ended active buffer for voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side and provides a channel with active buffering and level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using active I²C-bus buffer technology providing capacitive isolation, redriving and level shifting as well as disablement (isolation between source and sink) of the clock and data lines.

To provide the highest level of integration in external adapter (or: dongle) applications, PTN3381B includes an onboard 5 V DC regulator. Its output is designed to provide the required 5 V power supply to the DVI or HDMI connector, thereby eliminating the need for a separate external regulator. The on-board regulator needs only two external capacitors to operate, and its output is active whenever a valid 3.3 V is applied to the PTN3381B VDD pins.

The low-swing AC-coupled differential input signals to the PTN3381B typically come from a display source with multi-mode I/O, which supports multiple display standards, e.g., DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or HDMI v1.3a specification. By using PTN3381B, chip set vendors are able to implement such reconfigurable I/Os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set I/O pins low. See Figure 1.

The PTN3381B main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of DisplayPort Standard v1.1 and/or PCI Express Standard v1.1, and open-drain current-steering differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical specifications. The I²C-bus channel actively buffers as well as level-translates the DDC signals for optimal capacitive isolation. Its I²C-bus control block also provides for optional software HDMI dongle detect by issuing a predetermined code sequence upon a read command to an I²C-bus specified address. The PTN3381B also supports power-saving modes in order to minimize current consumption when no display is active or connected.

The PTN3381B is a fully featured HDMI as well as DVI level shifter. It is functionally equivalent to PTN3361B but provides an onboard 5 V regulator.

PTN3381B is powered from a single 3.3 V power supply consuming a small amount of power (100 mW typical without load at 5 V regulator output) and is offered in a 48-terminal HVQFN48 package

产品特点 Features

2.1 High-speed TMDS level shifting

Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals
Pin-programmable pre-emphasis feature
TMDS level shifting operation up to 1.65 Gbit/s per lane (165 MHz character clock)
TMDS level shifting operation up to 2.25 Gbit/s per lane (225 MHz character clock) using pre-emphasis feature
Integrated 50 Ω termination resistors for self-biasing differential inputs
Back-current safe outputs to disallow current when device power is off and monitor is on
Disable feature to turn off TMDS inputs and outputs and to enter low-power state

DDC level shifting

Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side)
Rise time accelerator on sink-side DDC ports
0 Hz to 400 kHz I²C-bus clock frequency
Back-power safe sink-side terminals to disallow backdrive current when power is off or when DDC is not enabled

HDMI dongle detect support

Incorporates I²C slave ROM
Responds to DDC read to address 81h with predetermined byte sequence
Feature enabled by pin DDET (must be enabled for correct operation in accordance with DisplayPort interoperability guideline)

HPD level shifting

HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or from 5 V on the sink side to 3.3 V on the source side
Integrated 200 kO pull-down resistor on HPD sink input guarantees ‘input LOW’ when no display is plugged in
Back-power safe design on HPD_SINK to disallow backdrive current when power is off

5 V DC voltage regulator

Generates 5 V for the DVI/HDMI connector from the 3.3 V DP_PWR pin supplied by the DisplayPort connector
Supports up to 75 mA of load current with an accuracy of ±300 mV
Only two external capacitors required
Eliminates need for an external 5 V regulator in dongle applications
Back drive protection on 5 V output
Short-circuit protection
Overcurrent protection

General

Power supply 3.3 V ± 10 %
ESD resilience to 4 kV HBM, 1 kV CDM
Support for optional HDMI dongle detection via DDC/I²C-bus channel
Power-saving modes (using output enable)
Back-current-safe design on all sink-side main link, DDC and HPD terminals
Transparent operation: no re-timing or software configuration required

应用

DisplayPort to HDMI adapters (must enable DDET)
DisplayPort to DVI adapters required to drive long cables

产品实物图

封装

型号	可订购的器件编号	订购码 (12NC)	产品状态	封装
PTN3381BBS	9352 878 25518	PTN3381BBS,518	量产	HVQFN48 (SOT619-1)

订货和供应

型号	订购码 (12NC)	可订购的器件编号	化学成分
PTN3381BBS	9352 878 25518	PTN3381BBS,518	PTN3381BBS

PTN3381BBS 技术支持

档案名称	标题	类型	格式
PTN3381BBS	Enhanced performance HDMI/DVI level shifter with voltage regulator, dongle detect support and active DDC buffer	Data sheet	pdf
AN10798	DisplayPort PCB layout guidelines	Application note	pdf
AN257	PTN products demo board documentation	Application note	pdf
AN257	PTN3310/3311 board	Application note	pdf
AN10462	SPI programming for Philips Bridge ICs	Application note	pdf
AN10485	SDA pin connection in SPI mode	Application note	pdf
AN10486	Automatic RS-485 address detection	Application note	pdf
AN10571	Sleep programming for NXP bridge ICs	Application note	pdf
AN10452	Interfacing Philips Bridge IC with Philips microcontroller	Application note	pdf
75015676	Low-power bridges for I2C or SPI to UART or IrDA or GPIO; NXP low-power bridges SC16IS750/52/60/62	Leaflet	pdf