MC10EP131:3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock
The MC10/100EP131 is a 6-bit fully differential register with common clock and single ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE + 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state.
技术特性
- 450 ps Typical Propagation Delay
- Maximum Frequency > 3.0 GHz Typical
- Asynchronous Master Reset
- 20 ps Skew Within Device, 35 ps Skew Device-To-Device
- PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
- Open Input Default State
- Safety Clamp on Inputs
- Pb-Free Packages are Available
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封装图 MARKING DIAGRAM
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC10EP131FAG |
Active |
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3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock |
LQFP-32 |
873A-02 |
2 |
Tray JEDEC |
250 |
|
| MC10EP131FAR2G |
Active |
|
3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock |
LQFP-32 |
873A-02 |
2 |
Tape and Reel |
2000 |
|
| MC10EP131MNG |
Active |
|
3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock |
QFN-32 |
488AM |
1 |
Tube |
74 |
|
| MC10EP131MNR4G |
Active |
|
3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock |
QFN-32 |
488AM |
1 |
Tape and Reel |
1000 |
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数据资料DataSheet下载
