MC14526B: Presettable 4-Bit Down Counters
The MC14526B binary counter is constructed with MOS P-channel and N-channel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded "0" state output for divide-by-N applications. In single stage applications the "0" output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide-by-N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock
技术特性
- Supply Voltage Range = 3.0 Vdc to 18 Vdc
- Logic Edge-Clocked Design - Incremented on Positive Transition of Clock or Negative Transition of Inhibit
- Asynchronous Preset Enable
- Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
- Pb-Free Packages are Available
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封装图 MARKING DIAGRAM
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订购信息 Ordering Information
产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价) |
类型 |
外形 |
类型 |
数量 |
MC14526BCPG |
Lifetime |
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Presettable 4-Bit Down Counters |
PDIP-16 |
648-08 |
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Tube |
500 |
$0.3733 |
MC14526BDWG |
Active |
|
Presettable 4-Bit Down Counters |
SOIC-16W |
751G-03 |
3 |
Tube |
47 |
$0.364 |
MC14526BDWR2G |
Active |
|
Presettable 4-Bit Down Counters |
SOIC-16W |
751G-03 |
3 |
Tape and Reel |
1000 |
$0.364 |
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