74LVC161284 Low Voltage CMOS Octal D-Type Latch Advenced Performance

The 74LVC161284 contains eight high speed non inverting bidirectional buffers and eleven control/status non-inverting buffers with open drain outputs fabricated in silicon gate C2MOS technology. It’s intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port Mode (ECP). The HD (Active HIGH) input pin enables the Cable port to switch from Open Drain to a high drive totem pole output, capable of sourcing 14mA on all thirteen buffer and 84mA on PERI LOGIC OUTPUT buffer. The DIR input determines the direction of data flow on the bidirectional buffers. DIR (Active HIGH) enables data flow from A port to B port. DIR (Active LOW) enables data flow from B port to A port. It is available in the commercial temperature range

技术特性

HIGH SPEED: tPD = 9ns (MAX.) at VCC = 3V
LOW POWER DISSIPATION:
- ICC=20μA (MAX) at VCC=3.6V TA=85˚C
TTL COMPATIBLE INPUTS
- VIH=2V (MIN) VIL=0.8(MAX)
OPERATING VOLTAGE RANGE:
- VCC(OPR) = 3.0V to 3.6V
A PORT HAVE STANDARD 4mA TOTEM POLE OUTPUT
B PORT HIGH DRIVE SOURCE/SINK CAPABILITY OF 14mA
SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE) AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR BIDIRECTIONAL PARALLEL COMMUNICATIONS BETWEEN PERSONAL COMPUTER ANT PRINTING PERIPHERALS
TRANSLATION CAPABILITY ALLOW OUTPUTS ON CABLE SIDE TO INTERFACE WITH 5V SIGNAL
PULL-UP RESISTOR INTEGRATED ON ALL OPEN-DRAIN OUTPUT ELIMINATE THE NEED FOR DISCRETE RESISTOR
REPLACE THE FUNCTION OF TWO 74LVC1284 DEVICES

74LVC161284 订购信息

订购型号	产品状态	美金价格	数量	封装	包装形式	温度范围	材料声明
74LVC161284MTR	Active			SO-48	Tape And Reel		74LVC161284MTR
74LVC161284TTR	Active			TSSOP 48	Tape And Reel		74LVC161284TTR

DATASHEET

描述	版本	大小
74LVC161284 : DS3319: Low voltage high speed IEEE1284 transceiver	1	218KB