74VHC138 3 to 8 Line Decoder (Inverting)

The 74VHC138 is an advanced high-speed CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

If the device is enabled, 3 binary select (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go to high.

Tree enable inputs are provided to ease cascade connection and application of address decoders for memory systems.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

技术特性

HIGH SPEED: tPD = 5.7ns (TYP.) at VCC = 5V
LOW POWER DISSIPATION:
- ICC = 4 μA (MAX.) at TA=25˚C
HIGH NOISE IMMUNITY:
- VNIH= VNIL= 28% VCC (MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
- |IOH| = IOL= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
- tPLH tPHL
OPERATING VOLTAGE RANGE:
- VCC(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138
IMPROVED LATCH-UP IMMUNITY

74VHC138 订购信息

订购型号	产品状态	美金价格	数量	封装	包装形式	温度范围	材料声明
74VHC138MTR	Active		1000	SO-16	Tape And Reel		74VHC138MTR
74VHC138TTR	Active		1000	TSSOP 16	Tape And Reel		74VHC138TTR

DATASHEET

描述	版本	大小
74VHC138 : 3 to 8 line decoder (inverting)	4	337KB