M48Z512AV 4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM
The M48Z512A/Y/V ZEROPOWER®RAM is a non-volatile, 4,194,304-bit static RAM organized as 524,288 words by 8 bits. The devices combine an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP module
技术特性
- Integrated, ultra low power SRAM, power-fail control circuit, and battery
- Conventional SRAM operation; unlimited WRITE cycles
- 10 years of data retention in the absence of power
- Automatic power-fail chip deselect and WRITE protection
- Two WRITE protect voltages: (VPFD= power-fail deselect voltage)
- M48Z512A: VCC= 4.75 to 5.5 V; 4.5 V ≤ VPFD≤ 4.75 V
- M48Z512AY: VCC= 4.5 to 5.5 V; 4.2 V ≤ VPFD≤ 4.5 V
- M48Z512AV: VCC= 3.0 to 3.6 V; 2.8 V ≤ VPFD≤ 3.0 V
- Battery internally isolated until power is applied
- Pin and function compatible with JEDEC standard 512 K x 8 SRAMs
- PMDIP32 is an ECOPACK®package
- RoHS compliant
- Lead-free second level interconnect
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功能框图
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M48Z512AV 订购信息
| 订购型号 |
产品状态 |
美金价格 |
数量 |
封装 |
包装形式 |
温度范围 |
材料声明 |
| M48Z512AV-85PM1 |
NRND |
|
1000 |
HYBRID 32L |
Tube |
|
M48Z512AV-85PM1 |
DATASHEET
| 描述 |
版本 |
大小 |
| M48Z512AV : DS1116: 4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM |
9 |
321KB |
APPLICATION NOTES
| 描述 |
版本 |
大小 |
| AN1012 : Predicting the battery life and data retention period of NVRAMs and serial RTCs |
4 |
440KB |
| AN1011 : Battery technology used in NVRAM and real-time clock (RTC) products from ST |
4 |
249KB |
| AN1009 : 'Negative undershoot' NVRAM data corruption |
1 |
34KB |
