SPC564A74B4 32 bit Power Architecture TM based MCU for Automotive Applications
The microcontroller’s e200z4 host processor core is built on Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).
技术特性
- 150 MHz e200z4 Power Architecture core
- Variable length instruction encoding (VLE)
- Superscalar architecture with 2 execution units
- Up to 2 integer or floating point instructions per cycle
- Up to 4 multiply and accumulate operations per cycle
- Memory organization
- 4 MB on-chip flash memory with ECC and Read While Write (RWW)
- 192 KB on-chip RAM with standby functionality (32 KB) and ECC
- 8 KB instruction cache (with line locking), configurable as 2- or 4-way
- 14 + 3 KB eTPU code and data RAM
- 5 × 4 crossbar switch (XBAR)
- External Bus Interface (EBI) with slave and master port
- Fail Safe Protection
- 16-entry Memory Protection Unit (MPU)
- CRC unit with 3 sub-modules
- Junction temperature sensor
- Interrupts
- Configurable interrupt controller (with NMI)
- Serial channels
- 3 × DSPI (2 of which support downstream Micro Second Channel [MSC])
- 3 × FlexCAN with 64 messages each
- 1 × FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC
- 1 × eMIOS
- 1 × eTPU2 (second generation eTPU)
- 1 × reaction module (6 channels with three outputs per channel)
- 2 enhanced queued analog-to-digital converters (eQADCs)
- Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers
- 688 ns minimum conversion time
- On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM)
- Nexus: Class 3+ for core; Class 1 for the eTPU
- JTAG (5-pin)
- Development Trigger Semaphore (DTS)
- Clock generation
- On-chip 4–40 MHz main oscillator
- On-chip FMPLL (frequency-modulated phase-locked loop)
- Up to 120 general purpose I/O lines
- Individually programmable as input, output or special function
- Programmable threshold (hysteresis)
- Power reduction mode: slow, stop and stand-by modes
- Flexible supply scheme
- 5 V single supply with external ballast
- Multiple external supply: 5 V, 3.3 V and 1.2 V
- Designed for LQFP176, LBGA208, PBGA324 and Known Good Die (KGD)
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管脚定义图
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SPC564A74B4 订购信息
订购型号 |
产品状态 |
美金价格 |
数量 |
封装 |
包装形式 |
温度范围 |
材料声明 |
SPC564A74B4CFAR |
Active |
|
1000 |
PBGA 324 23x23x1.82 |
Tape And Reel |
|
SPC564A74B4CFAR |
SPC564A74B4COBY |
Targer |
|
1000 |
PBGA 324 23x23x1.82 |
Tray |
|
SPC564A74B4COBY |
SPC564A74B4COBR |
Targer |
|
1000 |
PBGA 324 23x23x1.82 |
Tape And Reel |
|
SPC564A74B4COBR |
SPC564A74B4CFAY |
Active |
|
1000 |
PBGA 324 23x23x1.82 |
Tray |
|
SPC564A74B4CFAY |
DATASHEET
描述 |
版本 |
大小 |
SPC564A74B4 :DS6103: 32-bit MCU family built on the embedded Power Architecture® |
8 |
1408KB |
APPLICATION NOTES
描述 |
版本 |
大小 |
AN2577: Using the eTPU angle clock |
1 |
320KB |
AN3423: Shrinking the AUTOSAR OS: code size and performance optimizations |
1 |
116KB |
AN3348: Porting eTPU code to eTPU compiler build tools guides |
1 |
96KB |
AN4092: Hw recommendations for SPC564Axx / SPC563Mxx |
1 |
711KB |
AN4035: Flash programming through Nexus/JTAG |
1 |
635KB |
AN2618: eTPU host interface |
1 |
318KB |
AN3350: eTPU compiler tools |
1 |
1208KB |
AN3349: eTPU assembly converter |
1 |
123KB |
AN3044: ECU level diagnostic with SPC563Mx and SPC564Ax |
1 |
278KB |
ERRATA SHEETS
描述 |
版本 |
大小 |
ES0145: SPC564A74xx, SPC564A80xx device errata JTAG_ID = 0x1AE02041 |
5 |
117KB |
PROGRAMMING MANUALS
描述 |
版本 |
大小 |
PM0045: Signal processing engine (SPE) APU programming interface manual |
2 |
1873KB |
REFERENCE MANUALS
描述 |
版本 |
大小 |
RM0020: SPC56xx DSP function library 2 |
1 |
759KB |
RM0015: SPC563Mxx - 32-bit Power Architecture® based MCU with up to 1.5 Mbyte Flash and 111 Kbyte RAM memories |
7 |
10900KB |
USER MANUALS
描述 |
版本 |
大小 |
UM0715: SPC563MPrimerBasic |
1 |
266KB |
MARKETING BROCHURES