技术特性

• 16-bit CPU with DSP functions
  • 31.25ns instruction cycle time at 64MHz max CPU clock
  • Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator
  • Enhanced boolean bit manipulations
  • Single-cycle context switching support
• On-chip memories
  • 256 Kbyte Flash memory (32-bit fetch)
  • Single voltage Flash memories with erase/program controller and 100K erasing/programming cycles.
  • Up to 16 Mbyte linear address space for code and data (5 Mbytes with CAN or I²C)
  • 2 Kbyte internal RAM (IRAM)
  • 10/18 Kbyte extension RAM (XRAM)
  • Programmable external bus configuration & characteristics for different address ranges
  • Five programmable chip-select signals
  • Hold-acknowledge bus arbitration support
• Interrupt
  • 8-channel peripheral event controller for single cycle interrupt driven data transfer
  • 16-priority-level interrupt system with 56 sources, sampling rate down to 15.6ns
• Timers
  • Two multi-functional general purpose timer units with 5 timers
• Two 16-channel capture / compare units
• 4-channel PWM unit + 4-channel XPWM
• A/D converter
  • 24-channel 10-bit
  • 3 μs minimum conversion time
• Serial channels
  • Two synch. / asynch. serial channels
  • Two high-speed synchronous channels
  • One I²C standard interface
• 2 CAN 2.0B interfaces operating on 1 or 2 CAN busses (64 or 2x32 message, C-CAN version)
• Fail-safe protection
  • Programmable watchdog timer
  • Oscillator watchdog
• On-chip bootstrap loader
• Clock generation
  • On-chip PLL with 4 to 8 MHz oscillator
  • Direct or prescaled clock input
• Real time clock and 32 kHz on-chip oscillator
• Up to 111 general purpose I/O lines
  • Individually programmable as input, output or special function
  • Programmable threshold (hysteresis)
• Idle, power down and stand-by modes
• Single voltage supply: 5V ±10%

管脚定义图