技术特性

• High performance 16-bit CPU with DSP functions
  • 50ns instruction cycle time at 40 MHz max CPU clock
  • Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator
  • Enhanced boolean bit manipulations
  • Single-cycle context switching support
• Memory organization
  • 512 Kbyte on-chip Flash memory single voltage with erase/program controller (full performance, 32-bit fetch)
  • 100K erasing/programming cycles.
  • Up to 16 Mbyte linear address space for code and data (5 Mbytes with CAN or I²C)
  • 2 Kbyte on-chip internal RAM (IRAM)
  • 34 Kbyte on-chip extension RAM (XRAM)
  • Programmable external bus configuration and characteristics for different address ranges
  • 5 programmable chip-select signals
  • Hold-acknowledge bus arbitration support
• Interrupt
  • 8-channel peripheral event controller for single cycle interrupt driven data transfer
  • 16-priority-level interrupt system with 56 sources, sampling rate down to 25ns
• Timers
  • 2 multifunctional general purpose timer units with 5 timers
• Two 16-channel capture / compare units
• 4-channel PWM unit + 4-channel XPWM
• 24-channel A/D converter
  • 16-channel 10-bit, accuracy +/-2 LSB
  • 8-channel 10-bit, accuracy +/-5 LSB
  • 4.85µs Minimum conversion time
• Serial channels
  • 2 synch. / asynch. serial channels
  • 2 high-speed synchronous channels
  • I²C standard interface
• 2 CAN 2.0B interfaces operating on 1 or 2 CAN buses (64 or 2x32 messages, C-CAN version)
• Fail-safe protection
  • Programmable watchdog timer
  • Oscillator watchdog
• On-chip bootstrap loader
• Clock generation
  • On-chip PLL and 4 to 12 MHz oscillator
  • Direct or prescaled clock input
• Real time clock and 32 kHz on-chip oscillator
• Up to 111 general purpose I/O lines
  • Individually programmable as input, output or special function
  • Programmable threshold (hysteresis)
• Idle, power down and standby modes
• Single voltage supply: 5 V ±10% (embedded regulator for 1.8V core supply)
• Temperature range: -40 / +125 °C

功能框图