技术特性

• Memories
  • 8K or 16K Program memory (ROM or single voltage FLASH) with read-out protection and in-situ programming (remote ISP)
  • 256 bytes EEPROM Data memory (with read-out protection option in ROM devices)
  • 384 or 512 bytes RAM
• Clock, Reset and Supply Management
  • Enhanced reset system
  • Enhanced low voltage supply supervisor with 3 programmable levels
  • Clock sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
  • 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow
  • Beep and clock-out capabilities
• Interrupt Management
  • 10 interrupt vectors plus TRAP and RESET
  • 15 external interrupt lines (4 vectors)
• 44 or 32 I/O Ports
  • 44 or 32 multifunctional bidirectional I/O lines:
  • 21 or 19 alternate function lines
  • 12 or 8 high sink outputs
• 4 Timers
  • Configurable watchdog timer
  • Realtime base
  • Two 16-bit timers with: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes
• 2 Communications Interfaces
  • SPI synchronous serial interface
  • SCI asynchronous serial interface (LIN compatible)
• 1 Analog Peripheral
  • 8-bit ADC with 8 input channels (6 only on ST72334Jx, not available on ST72124J2)
• Instruction Set
  • 8-bit data manipulation
  • 63 basic instructions
  • 17 main addressing modes
  • 8 x 8 unsigned multiply instruction
  • True bit manipulation
• Development Tools
  • Full hardware/software development package

功能框图