STA662 AM/FM, DAB/DAB+/DMB-A, DRM multi-standard digital radio receiver

The STA662 from STMicroelectronics is a system-on-chip, based on multiple microcontroller and DSP cores, designed for demodulating and decoding the most common digital radio standards and the legacy AM/FM. The digital radio standards supported by STA662 are: DAB (ETSI EN 300 401), DAB+ (ETSI TS 102 563), DMB (ETSI TS 102 428), DRM (ETSI ES 201 980).

The STA662 implements the three main functions of a Eureka-147 DAB and DRM receiver specification.

The synchronization: including sampling clock and carrier frequency synchronization;The channel demodulation and decoding: including OFDM demodulation and convolutional decoding;The source decoding: consisting of audio and data decoding. The source decoding can be moved on an external application processor (a.k.a. SDEC - Source DECoder) so that the additional resources available on the STA662 IC can be used to implement a second DAB demodulation chain.

STA662 can demodulate in parallel two DAB streams and legacy AM or FM phase diversity stream.

AM and FM signal processing and audio functions are implemented on STA662 using dedicated resources, different from the resources used for the digital radio stream demodulation. FM phase diversity is implemented, as an alternative dual FM channels processing is possible, including the possibility to commute seamlessly from FM phase diversity to FM single tuner + FM background channels.To pursue the best combination in terms of current consumption, flexibility, system and device cost, these functions are implemented by a combination of hardware and software. Functional blocks which are standard and computationally intensive are implemented by custom logic. Functional blocks where flexibility is a key feature are implemented in software.

The STA662 combines it all into a single IC consisting of several hardware blocks implementing custom logic, an ARM946™ microcontroller one 24 bit DSP Emerald core and one 32 bit DSP xP70 core to guarantee the proper level of flexibility, low current consumption.

Such flexibility enables the STA662 to be ready for future evolution, including the possibility to implement new radio standards (i.e. HD-Radio™), and allows the implementation of specific and optional features.

Multiple interfaces such as SPI, UART, I²C and I2S, allow a flexible utilization of the device and several applications can be addressed, including T-DMB (video), by connecting an additional application co-processor (i.e. STA2165).

The STA662 implements a additional SDR-SDRAM interface thus allowing to implement memory-consuming firmware like DAB middleware and DAB/FM seamless switching.

To build a complete DAB/FM/AM receiver, the STA662 needs to be fed by the STA610 RF Multistandard front-end or from the STA610A RF AM/FM front-end. STA662 supports up to four RF FE connected in parallel.

The STA662 is assembled in TFBGA289 package

技术特性

General
- Multi-standard digital radio channel decoding
- Multi-standard digital radio source decoding (MPEG-1 AL II, AAC+, BSAC)
- AM/FM phase diversity
- Multiple streams parallel processing FM phase diversity plus two DAB channels
- Audio processing
- Audio streaming from SD Card, CD ROM (optional)
Supported radio systems
- AM, FM including phase diversity
- DAB, DAB+, DMB-Audio, DRM
- HD Radio™ (interface to co-processor STA680)
Hardware
- ARM946™ core running at 131.328 MHz
- STxP70 DSP core running at 262.256 or 131.328 MHz
- Emerald DSP core running at 131.328 MHz
- Multilayer AMBA architecture (6 AHB + 3 APB)
- DMA supporting 16 channels on 4 dedicated AHB layers
- VIC supporting vectored and standard interrupt requests
- Hardware support for conditional access (one-time programmable 768-bit memory)
- 2 internal PLLs: System PLL for cores and peripherals Fractional PLL for audio clocks input
Memories
- 64 KB Internal ROM
- 740 KB of Internal RAM available for cores
- 512 KB configurable DAB de-interleaving memory
- SPI Flash interface for application code loading running up to 16 MHz (optional SD/MMC)
- External SDR-SDRAM interface: 2 x 512 Mbit, 16-bit data bus
Turner interface
- 4 RF Front End LVDS interface
- 4 master SPI interface for tuners control
Other interfaces
- Audio interfaces (up to 8 independent and configurable I2S based on 45.6 kHz rate)
- Enhanced audio interface (fully configurable I2S)
- 2 S/PDIF receiver
- I²C interface
- 3 UART - GPIO interface (24 dedicated lines)
- Micro IF (based on 2 RX SPI + 2 TX SPI slave only + 4 audio clocks)
- 5 timers
- JTAG and ETM interfaces
Power supplies
- Core supply: 1.2 V
- I/O supply: 3.3 V
- Triple voltage I/O supply for host processor interface: 1.8 V / 2.5 V / 3.3 V
- Analog supply: 2.5 V (external or internal LDO)
Applications
- Multi-standard smart tuner module
- Multi-standard car-radio receiver
- Home receivers

管脚定义图

STA662 订购信息

订购型号	产品状态	美金价格	数量	封装	包装形式	温度范围	材料声明
STA662	Active		1000	TFBGA 289 15x15x1.2	Tray		STA662

DATASHEET

描述	版本	大小
STA662 :DB1695: AM/FM, DAB/DAB+/DMB-A, DRM multi-standard digital radio receiver	1	320KB