技术特性

• Compatible with the high-definition multimedia interface (HDMI) v1.3 digital interface
• Conforms to the transition minimized differential signaling (TMDS) voltage standard on input and output channels
• 340 MHz maximum clock speed operation supports all video formats with deep color at maximum refresh rates
• 3.4 Gbps data rate per channel
• Fully automatic adaptive equalizer for cables lengths up to 25 m
• Single supply VCC: 3.135 to 3.465 V
• ESD: > ± 5 KV HBM for all TMDS I/Os
• Integrated open-drain I²C buffer for display data channel (DDC)
• 5.3 V tolerant DDC and HPD I/Os
• Lock-up free operation of I²C bus
• 0 to 400 kHz clock frequency for I²C bus
• Low capacitance of all the channels
• Equalizer regenerates the incoming attenuated TMDS signal
• Buffer drives the TMDS outputs over long PCB track lengths
• Low output skew and jitter
• Tight input thresholds reduce bit error rates
• On-chip selectable 50 Ω input termination
• Low ground bounce
• Data and control inputs provide undershoot clamp diode
• Demonstration kit is available

功能框图