ADS5204-Q1 | |
Resolution(Bits) | 10 |
Sample Rate (max) | 40MSPS |
Architecture | Pipeline |
Power Consumption(Typ)(mW) | 275 |
SINAD(dB) | 60 |
SNR(dB) | 60.5 |
SFDR(dB) | 73 |
DNL(Max)(+/-LSB) | 1 |
INL(Max)(+/-LSB) | 1.5 |
No Missing Codes(Bits) | 10 |
ENOB(Bits) | 9.7 |
No. of Supplies | 1 |
Analog Voltage AV/DD(Min)(V) | 0 |
Analog Voltage AV/DD(Max)(V) | 3.6 |
Logic Voltage DV/DD(Min)(V) | 0 |
Logic Voltage DV/DD(Max)(V) | 3.6 |
Input Configuration Range | 2V (p-p) |
Rating | Automotive |
Pin/Package | 48TQFP |
# Input Channels | 2 |
Operating Temperature Range(°C) | -40 to 85 |
The ADS5204 is a dual 10-bit, 40 MSPS analog-to-digital converter (ADC). It simultaneously converts each analog input signal into a 10-bit, binary coded digital word up to a maximum sampling rate of 40 MSPS per channel. All digital inputs and outputs are 3.3-V TTL/CMOS compatible.
An innovative dual pipeline architecture implemented in a CMOS process and the 3.3-V supply results in very low power dissipation. In order to provide maximum flexibility, both top and bottom voltage references can be set from user-supplied voltages. Alternatively, if no external references are available, the on-chip internal references can be used. Both ADCs share a common reference to improve offset and gain matching. If external reference voltage levels are available, the internal references can be powered down independently from the rest of the chip, resulting in even greater power savings.
器件 | 状态 | 温度 (oC) | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
ADS5204IPFBRG4Q1 | ACTIVE | -40 to 85 | 16.10 | 1ku | TQFP (PFB) | 48 | 1000 | LARGE T&R | AZ5204Q |
ADS5204IPFBRQ1 | ACTIVE | -40 to 85 | 16.10 | 1ku | TQFP (PFB) | 48 | 1000 | LARGE T&R | AZ5204Q |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
ADS5204IPFBRG4Q1 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-3-260C-168 HR | ADS5204IPFBRG4Q1 | |
ADS5204IPFBRQ1 | TBD | CU NIPDAU | Level-2-220C-1 YEAR | ADS5204IPFBRQ1 |
名称 | 型号 | 公司 | 工具/软件类型 |
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