DIX4192 数字音频接口发送器
|
DIX4192 |
| Jitter(ps) |
0 |
| Sampling Rate(Max)(kHz) |
192 |
| Supply Voltage(s)(V) |
1.8 , 3.3 |
| Pin/Package |
48TQFP |
| Operating Temperature Range(°C) |
-40 to 85 |
DIX4192 说明
The DIX4192 is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The DIX4192 combines a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks.
The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports and DIT may be operated at sampling rates up to 216kHz. The DIR lock range includes sampling rates from 20kHz to 216kHz.
The DIX4192 is configured using on-chip control registers and data buffers, which are accessed through either a 4-wire serial peripheral interface (SPI) port, or a 2-wire Philips I2C bus interface
DIX4192 特性
- Digital Audio Interface Transmitter (DIT)
- Supports Sampling Rates Up to 216kHz
- Includes Differential Line Driver and CMOS Buffered Outputs
- Block-Sized Data Buffers for Both Channel Status and User Data
- Status Registers and Interrupt Generation for Flag and Error Conditions
- Digital Audio Interface Receiver (DIR)
- PLL Lock Range Includes Sampling Rates from 20kHz to 216kHz
- Includes Four Differential Input Line Receivers and an Input Multiplexer
- Bypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer Outputs
- Block-Sized Data Buffers for Both Channel Status and User Data
- Automatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats)
- Audio CD Q-Channel Sub-Code Decoding and Data Buffer
- Status Registers and Interrupt Generation for Flag and Error Conditions
- Low Jitter Recovered Clock Output
- User-Selectable Serial Host Interface: SPI™ or I2C™
- Provides Access to On-Chip Registers and Data Buffers
- Two Audio Serial Ports (Ports A and B)
- Synchronous Serial Interface to External Signal Processors, Data Converters, and Logic
- Slave or Master Mode Operation with Sampling Rates up to 216kHz
- Supports Left-Justified, Right-Justified, and Philips I2S™ Data Formats
DIX4192 芯片订购指南
| 器件 |
状态 |
温度 (oC) |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| DIX4192IPFB |
ACTIVE |
-40 to 85 |
4.35 | 1ku |
TQFP (PFB) | 48 |
250 | JEDEC TRAY (5+1) |
DIX4192I |
| DIX4192IPFBG4 |
ACTIVE |
-40 to 85 |
4.35 | 1ku |
TQFP (PFB) | 48 |
250 | JEDEC TRAY (5+1) |
DIX4192I |
| DIX4192IPFBR |
ACTIVE |
-40 to 85 |
3.95 | 1ku |
TQFP (PFB) | 48 |
1000 | LARGE T&R |
DIX4192I |
| DIX4192IPFBRG4 |
ACTIVE |
-40 to 85 |
3.95 | 1ku |
TQFP (PFB) | 48 |
1000 | LARGE T&R |
DIX4192I |
DIX4192 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| DIX4192IPFB |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-2-260C-1 YEAR |
|
DIX4192IPFB |
| DIX4192IPFBG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-2-260C-1 YEAR |
DIX4192IPFBG4 |
DIX4192IPFBG4 |
| DIX4192IPFBR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-2-260C-1 YEAR |
|
DIX4192IPFBR |
| DIX4192IPFBRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-2-260C-1 YEAR |
DIX4192IPFBRG4 |
DIX4192IPFBRG4 |
DIX4192 应用技术支持与电子电路设计开发资源下载
- DIX4192 数据资料 dataSheet 下载.PDF
- 模数规格和性能特性术语表 (Rev. A) (PDF 1993 KB)
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 高速数据转换 (PDF 1967 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF
1305 KB)
- Analog-to-Digital Converter Grounding Practices Affect System
Performance (PDF 56 KB)
- Principles of Data Acquisition and Conversion (PDF 50 KB)
- Interleaving Analog-to-Digital Converters (PDF 64 KB)
- What
Designers Should Know About Data Converter Drift (PDF 95 KB)
- Giving Delta-Sigma Converters a Gain Boost with a Front End
Analog Gain Stage (PDF 70 KB)
- Programming Tricks for Higher Conversion Speeds Utilizing Delta
Sigma Converters (PDF 105 KB)
DIX4192 工具与软件
