AT40K05

KeyValue
F.max (MHz):100 MHz
Max. Operating Freq. (MHz):100 MHz
Max I/O Pins:128
Speed:-2
Registers:256
Usable Gates:5K - 10K
Memory:2048

This 5,000 to 10,000-gate coprocessor is a fully PCI-compliant, SRAM-based FPGA with distributed 10-ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic® ability (partially or fully reconfigurable without loss of data), and automatic component generators. It has a 128 I/O count and supports a 5-V design. It can be used as a coprocessor for high-speed (DSP/processor-based) designs by implementing a variety of computation intensive, arithmetic functions. It is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC or Sun platform.

Ordering Code 订购信息
订购码封装操作范围载体类型
AT40K05-2BQJLQFP 144AA 144Industrial (A) (-40°C to 85°C)
DataSheet 数据手册
Application Note
Other
Overview
AT40K05/10/20/40 Complete (文件大小: 1.27MB, 55 页数, 修订版 E, 更新时间: 06/2013)
AT40K FPGA IP Core -- AT40K-FFT (文件大小: 138249, 9 页数, 修订版 B, 更新时间: 12/2008)
AT40K Check Function on Configuration (7 页数, 更新时间: 04/2001)
Conversion from Xilinx to Atmel FPGAs (8 页数, 更新时间: 07/2000)
Data Acquisition Systems Using Cache Logic FPGAs (5 页数, 更新时间: 09/1999)
Implementing a Single-coefficient Multiplier (文件大小: 114897, 5 页数, 更新时间: 03/2002)
Implementing Cache Logic with FPGAs (5 页数, 更新时间: 09/1999)
Replacement of a RAM with Atmel FreeRAM in Verilog-based Designs (9 页数, 更新时间: 08/2001)
AT40K FPGA Interactive Architecture Guide (更新时间: 04/1999)
HDLPlanner® Design Development Environment for HDL-based FPGA Designs (8 页数, 更新时间: 10/1999)