ATF16V8C

KeyValue
I/O Pins:20
Commercial tpd:5/7ns
Macrocells:8
Power Options:STANDARD
Registers:8
Usable Gates:150
F.max (MHz):5 MHz
Operating Voltage (Vcc):5
Temp. Range (deg C):-40 to 85
Temp. Range (deg C):0 to 70

A high-performance EECMOS programmable logic device (PLD) based on Atmel's proven electrically erasable flash memory technology. The device supports The device supports speeds down to 5ns and offers a 100 µA pin-controlled power-down mode option. All speed ranges are specified over the full 5V ± 10 percent range for industrial temperature ranges; 5V ± 5% for commercial range 5-volt devices. The device incorporates a superset of the generic architectures, to replace the 16R8 family and most 20-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three software-configurable modes of operation power highly complex logic functions and significantly reduce total system power and power costs, and enhance system reliability.

Ordering Code 订购信息
订购码封装操作范围载体类型
ATF16V8C-5JXPLCC 20J 20Commercial (0°C to 70°C)
ATF16V8C-7JUPLCC 20J 20Industrial (A) (-40°C to 85°C)
ATF16V8C-7PUPDIP 20P3 20Industrial (A) (-40°C to 85°C)
DataSheet 数据手册
  • ATF16V8C Complete(文件大小: 952KB, 24 页数, 修订版 I, 更新时间: 03/2014)
Application Note
Qualification
White Paper
ATF16V8C Complete (文件大小: 952KB, 24 页数, 修订版 I, 更新时间: 03/2014)
Atmel PLD Design Guidelines (12 页数, 更新时间: 09/2000)
Programming of Atmel PLDs (文件大小: 184KB, 4 页数, 修订版 A, 更新时间: 08/2015)
Saving Power with Atmel PLDs (7 页数, 更新时间: 09/2000)
Selecting Decoupling Capacitors for Atmel PLDs (4 页数, 更新时间: 09/1999)
Tips on Using Test Vectors for Atmel PLDs (20 页数, 更新时间: 09/1999)
Using Programmable Logic Devices (4 页数, 更新时间: 09/1999)
Using the Programmable Polarity Control (7 页数, 更新时间: 08/1999)
ATF16LV/V8C(Z) Reliability Qualification Report (文件大小: 73759, 7 页数, 更新时间: 07/2007)
Atmel CPLD Reference Designs (文件大小: 1660301, 17 页数, 更新时间: 01/2001)
Atmel CPLD Reference Designs (文件大小: 1660301, 17 页数, 更新时间: 01/2001)