Doc ID: DOC-620
Change
The IDCODE register is missing from Table 2-12 (Debug Register Groups for 0x1B Register Numbers). Add IDCODE as the last entry in the table as follows:
Register Name | Register Type | Direct Memory Address | Remarks |
---|---|---|---|
IDCODE | ID Code | 0x18037A | Reset value 0xX27811CB |
Doc ID: DOC-621
Change
Following Figure 2-3 (PRFM Register Bit Descriptions), add the following new section describing the IDCODE register. (For a better idea of how this information will be formatted in its final form, see ADSP-TS201 TigerSHARC Processor Hardware Reference page 2-83).
Silicon Version and ID Code (IDCODE) Register
The IDCODE register indicates processor model ID and silicon version. The IDCODE register's reset value is 0xV278 11CB (where V is version).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IDCODE31-28: Silicon Version
IDCODE27-0: IDCODE (0x278 11CB)1
1 The IDCODE27-0 field includes bits 27-0 (bits 15-0 not shown).
Figure 2-xx. IDCODE (Upper) Register Bit Descriptions
Doc ID: DOC-623
Change
Add the following info note after the bullet list:
(i) Emulation mode is used by debugger software (for example, the VisualDSP debugger with an emulator target). Information about emulation mode is particularly useful for developers of emulator software.
Doc ID: DOC-595
Change
The DMA request (DMARx asserted) signals indicated in Figure 5-18 and Figure 5-19 are not required. The following changes are needed:
Doc ID: DOC-640
Change
In table 6-10 (Data Throughput Rates), the formulas in the last two rows need to be updated. Change from:
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Doc ID: DOC-568
Change
In the Preface, the European Fax number is incorrect. Use +49-89-76903-157 instead.
In the Preface, the IP address of the FTP server is no longer valid. Use ftp://137.71.25.69 instead.
Last Update Date: 2007-03-29