Doc ID: DOC-1461
Change
Footnote 1 of Table 27, Maximum Duty Cycle for Input Transient Voltage, mistakenly omits the EXT_WAKE0 signal. The complete footnote is:
1 Applies to all signal balls with the exception of CLKIN, XTAL, EXT_WAKE0, VROUT/EXT_WAKE1, SCL, SDA, USB_DP, USB_DM, and USB_VBUS.
Doc ID: DOC-1127
Change
Add the following section to the data sheet.
Timer Clock Timing
Switching Characteristic = tTODP: Timer Output Update Delay After PPI_CLK High = 12 ns Max
Use the timing diagram from the ADSP-BF534/ADSP-BF536/ADSP-BF537 data sheet.
There are also three timing specifications (tTIS, tTIH, and tTOD ) that are missing in Table 39 (Timer Cycle Timing) on page 48. Additionally the unit of measure has changed.
Replace the current table with the following table.
Timer Cycle Timing Parameter VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 Unit Min Max Min Max Timing Characteristics tWL Timer Pulse Width Input Low1 1 x tSCLK 1 x tSCLK ns tWH Timer Pulse Width Input High1 1 x tSCLK 1 x tSCLK ns tTIS Timer Input Setup Time Before CLKOUT Low2 8.0 6.5 ns tTIH Timer Input Hold Time After CLKOUT Low2 1.5 1.5 ns Switching Characteristics tHTO Timer Pulse Width Output 1 x tSCLK (232 - 1) x tSCLK 1 x tSCLK (232 - 1) x tSCLK ns tTOD Timer Output Update Delay After CLKOUT High 7.5 6.5 ns (1) The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
(2) Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
Last Update Date: 2013-10-25
