Doc ID: DOC-1543
Change
The block diagram in Figure 4 contains the following errors:
CE should be CS.RST should be HOLD.WP is missing. It should appear under RST as a no connect (NC).Doc ID: DOC-1544
Change
The description of the timing requirement for tRST_IN_PWR is missing VDDFLASH. The correct timing requirement is as follows:
RESET Deasserted after the VDDINT, VDDEXT, VDDRTC, VDDMEM, VDDOTP, VDDFLASH, and CLKIN Pins are Stable and Within Specification.
Last Update Date: 2014-09-22
