SPI Interface removes the need for parallel conversion, logic traces and reduces GPIO channel count. Daisy chain mode removes additional logic traces when multiple devices are used. CRC error detection, Invalid Read/Write Address and SCLK Count Error detection ensures a robust digital interface. SIL Compatible. Minimum distortion.
The ADGS1412 contains four independent single-pole/single-throw (SPST) switches. An SPI interface controls the switches. The SPI interface has robust error detection features. These are CRC error detection, Invalid Read/Write Address detection and SCLK count error detection.
It is possible to daisy-chain multiple ADGS1412 devices together. This enables the configuration of multiple device with a minimal amount of digital lines. The ADGS1412 can also operate in burst mode to decrease the time between SPI commands.
The on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching signals.
iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments.
Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked.
The on-resistance profile is very flat over the full analog input range, which ensures good linearity and low distortion when switching audio signals.
产品特点和性能优势 | 开关和多路复用器 |
| 文档 | 备注 |
| ADGS1412: Serially-Controlled, 1.5 Ω On Resistance High Voltage, CMOS, Quad SPST Switch Preliminary Data Sheet (Rev. PrB) | PDF 426.57 K |
| 产品型号 | 封装 | 包装数量 | 温度范围 | 美金报价 100-499 | 美金报价 1000+ | RoHS |
|---|---|---|---|---|---|---|
| ADGS1412BCPZ 预发布 | LFCSP:LEADFRM CHIP SCALE | OTH 490 | -40 至 125至 | 0 | 0 | Y |
| ADGS1412BCPZ-RL7 预发布 | LFCSP:LEADFRM CHIP SCALE | REEL 1500 | -40 至 125至 | 0 | 0 | Y |
