AT40K10
| Key | Value |
|---|
| F.max (MHz): | 100 MHz |
|---|
| Max. Operating Freq. (MHz): | 100 MHz |
|---|
| Max I/O Pins: | 192 |
|---|
| Speed: | -2 |
|---|
| Registers: | 576 |
|---|
| Usable Gates: | 10K - 20K |
|---|
| Memory: | 4608 |
|---|
This 10,000 to 20,000-gate coprocessor is a fully PCI-compliant, SRAM-based FPGA with distributed 10-ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic® ability (partially or fully reconfigurable without loss of data), and automatic component generators. It has a 192 I/O count and supports a 5-V design. It can be used as a coprocessor for high-speed (DSP/processor-based) designs by implementing a variety of computation intensive, arithmetic functions. It is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC or Sun platform.
Ordering Code 订购信息| 订购码 | 封装 | 操作范围 | 载体类型 |
|---|
| AT40K10-W | Wafer Sales W | Industrial (A) (-40°C to 85°C) | |
| AT40K10-2DQU | PQFP 208Q1 208 | Industrial (A) (-40°C to 85°C) | |
DataSheet 数据手册
Application Note
- AT40K FPGA IP Core -- AT40K-FFT(文件大小: 138249, 9 页数, 修订版 B, 更新时间: 12/2008)
- AT40K Check Function on Configuration(7 页数, 更新时间: 04/2001)
- Conversion from Xilinx to Atmel FPGAs(8 页数, 更新时间: 07/2000)
- Data Acquisition Systems Using Cache Logic FPGAs(5 页数, 更新时间: 09/1999)
- Implementing a Single-coefficient Multiplier(文件大小: 114897, 5 页数, 更新时间: 03/2002)
- Implementing Cache Logic with FPGAs(5 页数, 更新时间: 09/1999)
- Replacement of a RAM with Atmel FreeRAM in Verilog-based Designs(9 页数, 更新时间: 08/2001)
Other
Overview
