| Key | Value |
|---|---|
| Temp. Range (deg C): | -55 to 125 |
| Max. Operating Freq. (MHz): | 400 MHz |
The ATU18 series of ULCs are fully suited for conversion of latest CPLDs and FPGAs. It supports within one ULC with 55Kbits to 847Kbits DPRAM and 45K to 1000K gates. Typically, the ULC die size is 50 percent smaller than the equivalent FPGA and requires significantly less operatingpower. Metal-level customization allows a DPRAM blocks compatibility with XiLINx® or Altera® blocks.
