UA1E

KeyValue
Temp. Range (deg C):-55 to 125

Amtel 0.35µm ULC Series with embedded DPRAM is well suited for conversion of large sized CPLDs and FPGAs.It supports within one ULC from 18 Kbits to 390 Kbits DPRAM and from 46 Kgates to 780 Kgates. Typically, ULC die size is 50 percent smaller than the equivalent FPGA die size and requires significantly less operating power. DPRAM blocks are compatible with XiLINx or Altera FPGA blocks.

DataSheet 数据手册
  • UA1E Complete(文件大小: 138709, 11 页数, 修订版 D, 更新时间: 04/2008)
Application Note
Brochures and Flyers
Other
Overview
UA1E Complete (文件大小: 138709, 11 页数, 修订版 D, 更新时间: 04/2008)
Design Portability for FPGA/ASIC Conversion (文件大小: 56600, 6 页数, 修订版 D, 更新时间: 03/2006)
FPGA/CPLD Conversion Service: ULC (文件大小: 914324, 8 页数, 修订版 C, 更新时间: 07/2005)
ULC Design Checklist (文件大小: 121776, 4 页数, 修订版 N, 更新时间: 06/2005)
ULC Conversion Process (8 页数, 更新时间: 12/2001)