CDK2308C：10-bit, 65MSPS, Dual ADC
The CDK2308 is a high performance, low power dual Analog-to-Digital Converters (ADC). The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range. Several idle modes with fast startup times exist. Each channel can independently be powered down and the entire chip can either be put in Standby Mode or Power Down mode. The different modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The CDK2308 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave and CMOS clock inputs.
技术特性- 10-bit resolution
- 65MSPS maximum sampling rate
- Ultra-low power dissipation: 65mW
- 61.6 dB SNR at Fin = 8MHz
- 1.8V core supply voltage
- 1.7V to 3.6V I/O supply voltage
- Parallel CMOS output
数据手册S | 产品应用- Medical imaging
- Portable test equipment
- Digital oscilloscope
- IF communications
| 规格 | 参数 | | 频道数量 | 2 | | 解析度(Bits) | 10 | | Sample Rate MSPS | 65 | | SNR dBFS | 61.6 | | SINAD dBFS | 61.6 | | SFDR dBc | 77 | | ENOB bits | 9.9 | | Power Consumption per CH mW | 33 | | Min Vs (V) | 1.7 | | Max Vs (V) | 2.0 | | View Full Specs | | | DNL | ±0.2 | | INL | ±0.6 | | Total Power Dissipation (mW) | 65 | | Input Type | Diff | | Architecture | Pipeline | | Temp Range °C | -40 to 85 | | 封装 | QFN-64 |
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订购型号
| 器件型号 | 封装编码 | 最低温度 | 最高温度 | 状态 |
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| CDK2308CILP64 | QFN-64 | -40 | 85 | Active |
| CEB2308 | Eval Board | | | Active |
