74AHC138D: 3至8线路解码器/解复用器;反相

74AHC138;74AHCT138是高速硅栅CMOS器件,与低功耗肖特基TTL (LSTTL)针脚兼容。其规格符合JEDEC标准No. 7A。

74AHC138;74AHCT138是3至8线路解码器/解复用器。其接受三个二进制加权地址输入(A0、A1和A2),处于使能状态时提供在被选中时为低电平的八个互斥输出(Y0至Y7)。

有三个使能输入:两个低电平有效(E1和E2)输入和一个高电平有效(E3)输入。除非E1和E2为低电平且E3为高电平,否则每个输出都将是高电平。

该多路使能功能只需凭借四个74AHC138;74AHCT138器件和一个反相器, 即能将该器件轻松并行扩展为32选1(5线路至32线路)解码器。通过将某个低电平有效使能输入用作数据输入以及将剩下的使能输入用作选通,74AHC138;74AHCT138可以用作一个八输出解复用器。未使用的使能输入必须恒定地连接到其相应的高电平或低电平有效状态。

74AHC138D: 产品结构框图
sot109-1_3d
数据手册 (1)
名称/描述Modified Date
3-to-8 line decoder/demultplexer; inverting (REV 4.0) PDF (119.0 kB) 74AHC_AHCT138 [English]02 Apr 2014
应用说明 (5)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Pin FMEA for AHC/AHCT family (REV 1.0) PDF (52.0 kB) AN11106 [English]04 Nov 2011
手册 (2)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
封装信息 (1)
名称/描述Modified Date
plastic small outline package; 16 leads; body width 3.9 mm (REV 1.0) PDF (192.0 kB) SOT109-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
SO16; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... (REV 4.0) PDF (210.0 kB) SOT109-1_118 [English]24 Apr 2013
支持信息 (2)
名称/描述Modified Date
Footprint for reflow soldering (REV 1.0) PDF (9.0 kB) SO-SOJ-REFLOW [English]08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (8.0 kB) SO-SOJ-WAVE [English]08 Oct 2009
IBIS
订购信息
型号状态Family功能VCC (V)说明Logic switching levelsOutput drive capability (mA)Package versiontpd (ns)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AHC138DActiveAHC(T)Decoders/demultiplexers2.0 - 5.5invertingCMOS+/- 8SOT109-14.4low-40~125939.752SO1616
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74AHC138DSOT109-1SO-SOJ-REFLOW SO-SOJ-WAVE
SO-SOJ-REFLOW SO-SOJ-WAVE
Reel 13" Q1/T1Active74AHC138D,118 (9352 629 99118)74AHC138D74AHC138Dweek 35, 200484.96.621.51E811
Bulk PackActive74AHC138D,112 (9352 629 99112)74AHC138D74AHC138Dweek 35, 200484.96.621.51E811
3-to-8 line decoder/demultplexer; inverting 74AHCT138PW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Pin FMEA for AHC/AHCT family 74AHC_T_245_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ahc138 IBIS model 74AHC138PW
plastic small outline package; 16 leads; body width 3.9 mm NPIC6C596A_Q100
Footprint for reflow soldering NPIC6C596A_Q100
Footprint for wave soldering NPIC6C596A_Q100
SO16; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... NPIC6C596A_Q100
74LVC138A
SA614A