74ALVC00BQ: 四路2输入与非门

74ALVC00是一款高性能、低功耗、低电压的硅栅CMOS器件,优于最先进的CMOS兼容TTL系列。

所有输入处的施密特触发器动作使电路容许较慢的输入上升和下降时间。

74ALVC00提供2输入与非功能。

符合JEDEC标准:

  • JESD8-7(1.65 V至1.95 V)
  • JESD8-5(2.3 V至2.7 V)
  • JESD8B/JESD36(2.7 V至3.6 V)

74ALVC00BQ: 产品结构框图
sot762-1_3d
数据手册 (1)
名称/描述Modified Date
Quad 2-input NAND gate (REV 3.0) PDF (181.0 kB) 74ALVC00 [English]16 May 2014
应用说明 (4)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
手册 (2)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x... (REV 1.0) PDF (187.0 kB) SOT762-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
Standard product orientation 12NC ending 115 (REV 3.0) PDF (108.0 kB) SOT762-1_115 [English]09 Apr 2013
IBIS
订购信息
型号状态Family功能VCC (V)Logic switching levels类型说明Output drive capability (mA)Package versiontpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74ALVC00BQActiveALVCNAND gates1.65 - 3.6TTLNAND gatesquad 2-input NAND gate+/- 24SOT762-12.11454low-40~8510318.371DHVQFN1414
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74ALVC00BQSOT762-1Reel 7" Q1/T1Active74ALVC00BQ,115 (9352 736 69115)AV0074ALVC00BQAlways Pb-free123.83.872.58E811
Quad 2-input NAND gate 74ALVC00PW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
alvc00 IBIS model 74ALVC00PW
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x... 74LV164_Q100
Standard product orientation 12NC ending 115 74LV164_Q100
74AVCM162836DGG
74LV164