74ALVCH16841DGG: 20位总线接口D型锁存器(三态)

74ALVCH16841具有两个10位D类锁存器,带用于每个锁存器的独立D类输入以及用于总线应用的三态输出。每个寄存器的两个部分由锁存器使能(nLE) 和输出使能(nOE)控制逻辑门独立控制。

nOE为低电平时,寄存器内的数据会出现在输出处。nOE为高电平时,输出处于高阻抗关断状态。nOE输入的操作不会影响触发器的状态。74ALVCH16841具有有源总线保持电路,可将闲置或浮动数据输入保持在有效逻辑电平。该功能无需外部上拉或下拉电阻。

74ALVCH16841DGG: 产品结构框图
Outline 3d SOT364-1
数据手册 (1)
名称/描述Modified Date
20-bit bus interface D-type latch (3-state) (REV 2.0) PDF (78.0 kB) 74ALVCH16841 [English]14 Mar 2014
应用说明 (6)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]15 Sep 1995
手册 (2)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic thin shrink small outline package; 56 leads; body width 6.1 mm (REV 1.0) PDF (506.0 kB) SOT364-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 4.0) PDF (248.0 kB) SOT364-1_118 [English]15 Apr 2013
支持信息 (1)
名称/描述Modified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS
订购信息
型号状态FamilyVCC (V)功能Logic switching levels说明Package versionOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74ALVCH16841DGGActiveALVC2.3 - 3.6Latches/registered driversLVTTL20-bit D-type transparent latch with bus hold (3-state)SOT364-1+/- 242.420low-40~859321.0TSSOP5656
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74ALVCH16841DGGSOT364-1SSOP-TSSOP-VSO-WAVETube in DrypackActive74ALVCH16841DGGS (9352 590 90512)ALVCH1684174ALVCH16841DGGAlways Pb-free123.83.872.58E811
Reel 13" Q1/T1 in DrypackActive74ALVCH16841DGGY (9352 590 90518)ALVCH1684174ALVCH16841DGGAlways Pb-free123.83.872.58E811
Bulk PackDiscontinued74ALVCH16841DGG:11 (9352 590 90112)ALVCH1684174ALVCH16841DGGweek 2, 2006123.83.872.58E811
Reel 13" Q1/T1Withdrawn74ALVCH16841DGG,11 (9352 590 90118)ALVCH1684174ALVCH16841DGGweek 2, 2006123.83.872.58E811
20-bit bus interface D-type latch (3-state) 74ALVCH16841DGG
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
A metastability primer 74AHC573PW
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
alvch16841 IBIS model 74ALVCH16841DGG
plastic thin shrink small outline package; 56 leads; body width 6.1 mm pcf8576d_automotive
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... pcf8576d_automotive
74ALVCH16841DGG
74LVT16652A