74AUP2G08GT: 低功耗双路2输入与门

74AUP2G08提供双路2输入与功能。

所有输入处的施密特触发器动作使电路容许整个0.8 V至3.6 V VCC范围内较慢的输入上升和下降时间。

该器件可确保整个0.8 V至3.6 V VCC范围内的极低静态和动态功耗。

该器件完全适合使用IOFF的局部掉电应用。IOFF电路可禁用输出,防止断电时破坏性回流电流通过该器件。

74AUP2G08GT: 产品结构框图
74AUP2G08GT: 应用结构框图
74AUP2G08GT: 应用结构框图
Outline 3d SOT833-1
数据手册 (1)
名称/描述Modified Date
Low-power dual 2-input AND gate (REV 7.0) PDF (276.0 kB) 74AUP2G08 [English]18 Jan 2013
应用说明 (4)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English]30 Dec 2010
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
手册 (3)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm (REV 1.0) PDF (201.0 kB) SOT833-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
Standard product orientation 12NC ending 115 (REV 3.0) PDF (88.0 kB) SOT833-1_115 [English]05 Apr 2013
支持信息 (1)
名称/描述Modified Date
MAR_SOT833 Topmark (REV 1.0) PDF (75.0 kB) MAR_SOT833 [English]03 Jun 2013
IBIS
订购信息
型号状态Family功能VCC (V)说明类型Logic switching levelsOutput drive capability (mA)Package versiontpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP2G08GTActiveAUPAND gates1.1 - 3.6dual 2-input AND gateAND gatesCMOS+/- 1.9SOT833-18.2702ultra low-40~1253276.1157XSON88
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74AUP2G08GTSOT833-1Reel 7" Q1/T1Active74AUP2G08GT,115 (9352 807 12115)p0874AUP2G08GTAlways Pb-free0.03.293.04E811
Low-power dual 2-input AND gate 74AUP2G08GT
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
MicroPak soldering information NTS0102_Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT833 Topmark NCX2222
aup2g08 IBIS model 74AUP2G08GT
plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm NCX2222
Standard product orientation 12NC ending 115 NCX2222
74LVC2G08
74AVCM162836DGG
XC7WT14