74AUP2G132GD: 低功耗双路2输入与非施密特触发器

74AUP2G132提供双路2输入与非施密特触发器功能,其接受标准输入信号。该类器件能够将缓慢变化的输入信号转换成清晰无抖动的输出信号。

该器件可确保整个0.8 V至3.6 V VCC范围内的极低静态和动态功耗。

该器件完全适合使用IOFF的局部掉电应用。IOFF电路可禁用输出,防止掉电时破坏性回流电流通过该器件。

输入针对正向和负向信号在不同点进行切换。正电压VT+和负电压VT-之差定义为输入迟滞电压VH.

74AUP2G132GD: 产品结构框图
74AUP2G132GD: 应用结构框图
74AUP2G132GD: 应用结构框图
Outline 3d SOT996-2
数据手册 (1)
名称/描述Modified Date
low-power dual 2-input NAND Schmitt trigger (REV 7.0) PDF (290.0 kB) 74AUP2G132 [English]08 Feb 2013
应用说明 (4)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English]30 Dec 2010
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
手册 (3)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm (REV 1.0) PDF (190.0 kB) SOT996-2 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
XSON8(U); Reel pack, Reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... (REV 5.0) PDF (200.0 kB) SOT996-2_125 [English]02 May 2013
IBIS
订购信息
型号状态Family功能VCC (V)类型说明Logic switching levelsOutput drive capability (mA)Package versiontpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP2G132GDActiveAUPSchmitt-triggers1.1 - 3.6NAND gatesdual 2-input NAND gate Schmitt-triggerCMOS+/- 1.9SOT996-210702ultra Low-40~12561080.8271XSON88
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74AUP2G132GDSOT996-2Reel 7" Q3/T4, ReverseActive74AUP2G132GD,125 (9352 883 27125)aE274AUP2G132GDAlways Pb-free0.03.293.04E811
low-power dual 2-input NAND Schmitt trigger 74AUP2G132GT
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
MicroPak soldering information NTS0102_Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
aup2g132 IBIS model 74AUP2G132GT
plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm 74AHC_T_3G14_Q100
XSON8(U); Reel pack, Reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... 74AHC_T_3G14_Q100
74AUP2G132
74AVCM162836DGG
74AUP2G132
LM75B