74AUP2G14GS: 低功耗双路施密特触发反相器

74AUP2G14提供两个带施密特触发动作的反相缓冲器,其接受标准输入信号。该类器件能将缓慢变化的输入信号转换成清晰无抖动的输出信号。

该器件可确保整个0.8 V至3.6 V VCC范围内的极低静态和动态功耗。

该器件完全适合使用IOFF的局部掉电应用。IOFF电路可禁用输出,防止掉电时破坏性回流电流通过该器件。

输入针对正向和负向信号在不同点进行切换。 正电压VT+和负电压VT-之差定义为输入迟滞电压VH.

74AUP2G14GS: 产品结构框图
sot1202_3d
数据手册 (1)
名称/描述Modified Date
Low-power dual Schmitt trigger inverter (REV 6.0) PDF (240.0 kB) 74AUP2G14 [English]17 Sep 2015
应用说明 (2)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
手册 (3)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm (REV 1.0) PDF (192.0 kB) SOT1202 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1202_132 [English]04 Apr 2013
支持信息 (1)
名称/描述Modified Date
MAR_SOT1202 Topmark (REV 1.0) PDF (49.0 kB) MAR_SOT1202 [English]03 Jun 2013
IBIS
订购信息
型号状态FamilyVCC (V)功能说明Logic switching levelsOutput drive capability (mA)Package versionfmax (MHz)tpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP2G14GSActiveAUP1.1 - 3.6Buffers/inverters/driversSchmitt-triggerCMOS+/- 1.9SOT1202704.72ultra low-40~12527214.8177XSON66
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期MSLMSL LF
74AUP2G14GSSOT1202Reel 7" Q1/T1, Q3/T4Active74AUP2G14GS,132 (9352 928 87132)pK74AUP2G14GSAlways Pb-free11
Low-power dual Schmitt trigger inverter 74AUP2G14GX
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT1202 Topmark NCX2200GS
aup2g14 IBIS model 74AUP2G14GW
XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm NCX2200GS
Reversed product orientation 12NC ending 132 NTS0101
74AVCM162836DGG
74LVC2G17