74AUP2G97GF: Low-power dual PCB configurable multiple function gate

The 74AUP2G97 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

74AUP2G97GF: 产品结构框图

Outline 3d SOT1081-2

数据手册 (1)

名称/描述	Modified Date
Low-power dual PCB configurable multiple function gate (REV 2.0) PDF (221.0 kB) 74AUP2G97 [English]	02 Dec 2015

手册 (2)

名称/描述	Modified Date
NXP® Dual PCB Configurable Logic (REV 1.0) PDF (3.0 MB) 75017615 [English]	07 Nov 2014
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]	13 Oct 2014

选型工具指南 (2)

名称/描述	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

封装信息 (1)

名称/描述	Modified Date
plastic extremely thin small outline package; no leads; 10 terminals (REV 1.0) PDF (160.0 kB) SOT1081-2 [English]	08 Feb 2016

IBIS

74AUP2G98 IBIS model (REV 1.0) ibs AUP2G97 4/3/2015

订购信息

型号	状态	Family	功能	V_CC (V)	类型	Logic switching levels	说明	Package version	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74AUP2G97GF	Active	AUP	dual configurable gate; Schmitt trigger	1.1 - 3.6	Configurable gates	CMOS	Configurable	SOT1081-2	+/- 1.9	8.7	70	2	ultra low	-40~125	192	97.0		XSON10	10