74AUP2G97GU: Low-power dual PCB configurable multiple function gate
The 74AUP2G97 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND.
This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
74AUP2G97GU: 产品结构框图
sot1160-1_3d
数据手册 (1)
| 名称/描述 | Modified Date |
|---|---|
| Low-power dual PCB configurable multiple function gate (REV 2.0) PDF (221.0 kB) 74AUP2G97 [English] | 02 Dec 2015 |
手册 (2)
| 名称/描述 | Modified Date |
|---|---|
| NXP® Dual PCB Configurable Logic (REV 1.0) PDF (3.0 MB) 75017615 [English] | 07 Nov 2014 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
选型工具指南 (2)
| 名称/描述 | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
封装信息 (1)
| 名称/描述 | Modified Date |
|---|---|
| plastic, extremely thin quad flat package; no leads; 10 terminals (REV 1.0) PDF (207.0 kB) SOT1160-1 [English] | 08 Feb 2016 |
包装 (1)
| 名称/描述 | Modified Date |
|---|---|
| Standard product orientation 12NC ending 115 (REV 2.0) PDF (97.0 kB) SOT1160-1_115 [English] | 04 Apr 2013 |
IBIS
- 74AUP2G98 IBIS model (REV 1.0) ibs AUP2G97 4/3/2015
订购信息
| 型号 | 状态 | Family | 功能 | VCC (V) | 说明 | Logic switching levels | 类型 | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G97GU | Active | AUP | dual configurable gate; Schmitt trigger | 1.1 - 3.6 | Configurable | CMOS | Configurable gates | +/- 1.9 | SOT1160-1 | 8.7 | 70 | 2 | ultra low | -40~125 | 142 | 48.0 | XQFN10 | 10 |
封装环保信息
| 产品编号 | 封装说明 | Outline Version | 回流/波峰焊接 | 包装 | 产品状态 | 部件编号订购码 (12NC) | Marking | 化学成分 | RoHS / 无铅 / RHF | 无铅转换日期 | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G97GU | | SOT1160-1 | Reel 7" Q1/T1 | Active | 74AUP2G97GUX (9353 044 84115) | aV | 74AUP2G97GU |    | Always Pb-free | 1 | 1 |
- NXP® Dual PCB Configurable Logic 74AUP2G98GU
- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- 74AUP2G98 IBIS model 74AUP2G97GU
- plastic, extremely thin quad flat package; no leads; 10 terminals NX5L2750CGU
- Standard product orientation 12NC ending 115 NX5L2750CGU
- 74AVCM162836DGG
- NTS0103GU10
