74AUP3G07DC: Low-power triple buffer with open-drain output
The 74AUP3G07 is a triple non-inverting buffer with open-drain output. The output of the
device is an open drain and can be connected to other open-drain outputs to implement
active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and
fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow
current through the device when it is powered down.
Complies with JEDEC standards: - JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
| 74AUP3G07DC: 产品结构框图 Outline 3d SOT765-1 |
数据手册 (1)
选型工具指南 (2)
封装信息 (1)
包装 (1)
IBIS
订购信息
| 型号 | 状态 | Family | VCC (V) | 功能 | Logic switching levels | 说明 | Output drive capability (mA) | Package version | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|
| 74AUP3G07DC | Active | AUP | | Buffers/inverters/drivers | | open-drain | | SOT765-1 | | | | | 203 | 34.1 | 113 | VSSOP8 | 8 |
封装环保信息
| 产品编号 | 封装说明 | Outline Version | 回流/波峰焊接 | 包装 | 产品状态 | 部件编号订购码 (12NC) | Marking | 化学成分 | RoHS / 无铅 / RHF | 无铅转换日期 | MSL | MSL LF |
|---|
| 74AUP3G07DC | | SOT765-1 | | Reel 7" Q3/T4, Reverse | Active | 74AUP3G07DCH
(9352 806 98125) | Standard Marking | 74AUP3G07DC |    | Always Pb-free | 1 | 1 |
