74AUP3G07GM: Low-power triple buffer with open-drain output

The 74AUP3G07 is a triple non-inverting buffer with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Complies with JEDEC standards:

  • JESD8-12 (0.8 V to 1.3 V)
  • JESD8-11 (0.9 V to 1.65 V)
  • JESD8-7 (1.2 V to 1.95 V)
  • JESD8-5 (1.8 V to 2.7 V)
  • JESD8-B (2.7 V to 3.6 V)

74AUP3G07GM: 产品结构框图
Outline 3d SOT902-2
数据手册 (1)
名称/描述Modified Date
Low-power triple buffer with open-drain output (REV 2.0) PDF (188.0 kB) 74AUP3G07 [English]05 Oct 2016
应用说明 (2)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
手册 (3)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
Plastic extremely thin quad flat package; no leads; 8 terminals (REV 1.3) PDF (206.0 kB) SOT902-2 [English]14 Jul 2016
包装 (1)
名称/描述Modified Date
XQFN8(U); Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... (REV 1.0) PDF (201.0 kB) SOT902-2_125 [English]02 May 2013
IBIS
订购信息
型号状态FamilyVCC (V)功能说明Logic switching levelsPackage versionOutput drive capability (mA)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP3G07GMActiveAUPBuffers/inverters/driversopen drainSOT902-2XQFN88
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期MSLMSL LF
74AUP3G07GMSOT902-2Reel 7" Q3/T4, ReverseActive74AUP3G07GM,125 (9352 814 42125)Standard Marking74AUP3G07GMAlways Pb-free11
Low-power triple buffer with open-drain output 74AUP3G07GT
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
74AUP3G07 IBIS model 74AUP3G07GT
Plastic extremely thin quad flat package; no leads; 8 terminals pca9509agm
XQFN8(U); Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... pca9509agm
74AVCM162836DGG
74LVC3G17