74AUP3G16DC: Low-power triple buffer
The 74AUP3G16 is a triple buffer.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and
fall times.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing a damaging backflow
current through the device when it is powered down.
Outline 3d SOT765-1
数据手册 (1)
封装信息 (1)
包装 (1)
IBIS
订购信息
| 型号 | 状态 | Family | VCC (V) | 说明 | Logic switching levels | Output drive capability (mA) | fmax (MHz) | No of bits | Power dissipation considerations | tpd (ns) | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins | Package version |
|---|
| 74AUP3G16DC | Active | AUP | 1.1 - 3.6 | triple buffer | CMOS | +/- 1.9 | 70 | 3 | ultra low | 3.9 | -40~125 | 203 | 34.1 | 113 | VSSOP8 | 8 | SOT765-1 |
封装环保信息
| 产品编号 | 封装说明 | Outline Version | 回流/波峰焊接 | 包装 | 产品状态 | 部件编号订购码 (12NC) | Marking | 化学成分 | RoHS / 无铅 / RHF | 无铅转换日期 | MSL | MSL LF |
|---|
| 74AUP3G16DC | | SOT765-1 | | Reel 7" Q3/T4, Reverse | Active | 74AUP3G16DCH
(9353 075 57125) | Standard Marking | 74AUP3G16DC |    | Always Pb-free | 1 | 1 |
