74AUP3G17DC: Low-power triple Schmitt trigger
The 74AUP3G17 provides three Schmitt trigger buffers. It is capable of transforming
slowly changing input signals into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow
current through the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The
difference between the positive voltage VT+ and the negative voltage
VT- is defined as the input hysteresis voltage VH.
Outline 3d SOT765-1
数据手册 (1)
封装信息 (1)
包装 (1)
IBIS
订购信息
| 型号 | 状态 | Family | VCC (V) | Logic switching levels | 说明 | Output drive capability (mA) | fmax (MHz) | No of bits | Power dissipation considerations | tpd (ns) | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins | Package version |
|---|
| 74AUP3G17DC | Active | AUP | 1.1 - 3.6 | CMOS | triple buffer Schmitt-trigger | +/- 1.9 | 70 | 3 | ultra low | 4.7 | -40~125 | 203 | 34.1 | 113 | VSSOP8 | 8 | SOT765-1 |
封装环保信息
| 产品编号 | 封装说明 | Outline Version | 回流/波峰焊接 | 包装 | 产品状态 | 部件编号订购码 (12NC) | Marking | 化学成分 | RoHS / 无铅 / RHF | 无铅转换日期 | MSL | MSL LF |
|---|
| 74AUP3G17DC | | SOT765-1 | | Reel 7" Q3/T4, Reverse | Active | 74AUP3G17DCH
(9352 806 97125) | Standard Marking | 74AUP3G17DC |    | Always Pb-free | 1 | 1 |
