74LVC125APW: 四路缓冲器/线路驱动器,带5 V容压输入/输出;3态

74LVC125A由四个带3态输出(nY)的非反相缓冲器/线路驱动器组成,由输出使能输入(nOE)进行控制。nOE处的高电平使输出呈高阻抗关断状态。

输入可通过3.3 V或5 V器件进行驱动。禁用时,可以向输出施加高达5.5 V的电压。

74LVC125APW: 产品结构框图
Outline 3d SOT402-1
数据手册 (1)
名称/描述Modified Date
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state (REV 7.0) PDF (119.0 kB) 74LVC125A [English]11 Apr 2013
应用说明 (5)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English]04 Feb 2011
Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English]05 Feb 2002
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]15 Sep 1995
封装信息 (1)
名称/描述Modified Date
plastic thin shrink small outline package; 14 leads; body width 4.4 mm (REV 1.0) PDF (285.0 kB) SOT402-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 1.0) PDF (217.0 kB) SOT402-1_118 [English]08 Apr 2013
支持信息 (1)
名称/描述Modified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS
SPICE
订购信息
型号状态FamilyVCC (V)功能Logic switching levels说明Output drive capability (mA)Package versionfmax (MHz)No of bitsPower dissipation considerationstpd (ns)Tamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVC125APWActiveLVC1.2 - 3.6Buffers/inverters/driversCMOS/LVTTLquad buffer/line driver (3-state)+/- 24SOT402-11754low2.4-40~1251428.1387964601769968.3603185840708TSSOP1414
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74LVC125APWSOT402-1SSOP-TSSOP-VSO-WAVEReel 13" Q1/T1Active74LVC125APW,118 (9352 317 20118)LVC125A74LVC125APWweek 10, 2005123.83.872.58E811
Bulk PackActive74LVC125APW,112 (9352 317 20112)LVC125A74LVC125APWweek 10, 2005123.83.872.58E811
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state 74LVC125APW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Pin FMEA for LVC family 74LVC1G123_Q100
Power considerations when using CMOS and BiCMOS logic devices 74AHCT244PW
Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
lvc125a IBIS model 74LVC125APW
lvc Spice model 74LVC3G17GT
plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74LV164_Q100
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... 74LV164_Q100
74LVT_H_125
74LV164