74LVC126ABQ: 四路缓冲器/线路驱动器，带5 V容压输入/输出；3态 _ BDTIC 中国领先电子元器件代理商

74LVC126ABQ: 四路缓冲器/线路驱动器，带5 V容压输入/输出；3态

74LVC126A由四个带3态输出的非反相缓冲器/线路驱动器组成，由输出使能输入(nOE)进行控制。nOE处的低电平使输出呈高阻抗关断状态。

输入可通过3.3 V或5 V器件进行驱动。禁用时，可以向输出施加高达5.5 V的电压。

74LVC126ABQ: 产品结构框图

sot762-1_3d

数据手册 (1)

名称/描述	Modified Date
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state (REV 8.0) PDF (131.0 kB) 74LVC126A [English]	08 Apr 2014

应用说明 (5)

名称/描述	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English]	04 Feb 2011
Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English]	05 Feb 2002
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]	15 Sep 1995

封装信息 (1)

名称/描述	Modified Date
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x... (REV 1.0) PDF (187.0 kB) SOT762-1 [English]	08 Feb 2016

包装 (1)

名称/描述	Modified Date
Standard product orientation 12NC ending 115 (REV 3.0) PDF (108.0 kB) SOT762-1_115 [English]	09 Apr 2013

IBIS

lvc126a IBIS model (REV 1.0) ibs LVC126A 4/7/2013

SPICE

lvc Spice model (REV 1.0) ZIP LVC 5/7/2013

订购信息

型号	状态	Family	功能	V_CC (V)	说明	Logic switching levels	Package version	Output drive capability (mA)	f_max (MHz)	No of bits	t_pd (ns)	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74LVC126ABQ	Active	LVC	Buffers/inverters/drivers	1.2 - 3.6	quad buffer/line driver (3-state)	CMOS/LVTTL	SOT762-1	+/- 24	175	4	2.4	low	-40~125	107	21.9	75	DHVQFN14	14

封装环保信息

产品编号	封装说明	Outline Version	回流/波峰焊接	包装	产品状态	部件编号订购码 (12NC)	Marking	化学成分	RoHS / 无铅 / RHF	无铅转换日期	EFR	IFR(FIT)	MTBF（小时）	MSL	MSL LF
74LVC126ABQ		SOT762-1		Reel 7" Q1/T1	Active	74LVC126ABQ,115 (9352 740 82115)	VC126	74LVC126ABQ		Always Pb-free	123.8	3.87	2.58E8	1	1

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state 74LVC126APW

Sorting through the low voltage logic maze 74LVC_H_245A_Q100

Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100

Pin FMEA for LVC family 74LVC1G123_Q100

Power considerations when using CMOS and BiCMOS logic devices 74AHCT244PW

Interfacing 3 Volt and 5 Volt Applications 74LVC377PW

lvc126a IBIS model 74LVC126APW

lvc Spice model 74LVC3G17GT

plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x... 74LV164_Q100

Standard product orientation 12NC ending 115 74LV164_Q100

74LVC126A

74LV164

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