74LVT02D: 3.3 V Quad 2-input NOR gate _ BDTIC 中国领先电子元器件代理商

74LVT02D: 3.3 V Quad 2-input NOR gate

The 74LVT02 is a quad 2-input NOR gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

74LVT02D: 产品结构框图

sot108-1_3d

数据手册 (1)

名称/描述	Modified Date
3.3 V Quad 2-input NOR gate (REV 2.0) PDF (91.0 kB) 74LVT02 [English]	15 Aug 1996

应用说明 (7)

名称/描述	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]	13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013
Test Fixtures for High Speed Logic (REV 1.0) PDF (341.0 kB) AN203 [English]	02 Apr 1998
Transmission Lines and Terminations with Philips Advanced Logic Families (REV 1.0) PDF (217.0 kB) AN246 [English]	01 Feb 1998
LVT (Low Voltage Technology) and ALVT (Advanced LVT) (REV 1.0) PDF (133.0 kB) AN243 [English]	01 Jan 1998

选型工具指南 (2)

名称/描述	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

封装信息 (1)

名称/描述	Modified Date
plastic small outline package; 14 leads; body width 3.9 mm (REV 1.0) PDF (166.0 kB) SOT108-1 [English]	08 Feb 2016

包装 (1)

名称/描述	Modified Date
SO14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... (REV 4.0) PDF (207.0 kB) SOT108-1_118 [English]	08 Apr 2013

支持信息 (2)

名称/描述	Modified Date
Footprint for reflow soldering (REV 1.0) PDF (9.0 kB) SO-SOJ-REFLOW [English]	08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (8.0 kB) SO-SOJ-WAVE [English]	08 Oct 2009

IBIS

lvt02 IBIS model (REV 1.0) ibs LVT02 4/7/2013

SPICE

lvt Spice model (REV 1.0) ZIP LVT 5/7/2013

订购信息

型号	状态	Family	功能	V_CC (V)	类型	Logic switching levels	说明	Output drive capability (mA)	Package version	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74LVT02D	Active	LVT	NOR gates	2.7 - 3.6	NOR gates	TTL	quad 2-input NOR gate	-32/+64	SOT108-1	2.8	150	4	medium	-40~85	108	20.3	67	SO14	14

封装环保信息

产品编号	封装说明	Outline Version	回流/波峰焊接	包装	产品状态	部件编号订购码 (12NC)	Marking	化学成分	RoHS / 无铅 / RHF	无铅转换日期	EFR	IFR(FIT)	MTBF（小时）	MSL	MSL LF
74LVT02D		SOT108-1	SO-SOJ-REFLOW SO-SOJ-WAVE SO-SOJ-REFLOW SO-SOJ-WAVE	Reel 13" Q1/T1	Active	74LVT02D,118 (9352 089 50118)	74LVT02D	74LVT02D		week 5, 2004	70.8	1.33	7.52E8	1	1
74LVT02D		SOT108-1	SO-SOJ-REFLOW SO-SOJ-WAVE SO-SOJ-REFLOW SO-SOJ-WAVE	Bulk Pack	Active	74LVT02D,112 (9352 089 50112)	74LVT02D	74LVT02D		week 5, 2004	70.8	1.33	7.52E8	1	1