AX2061: LCD Driver for Low Multiplex Rates
The AX2061 contains an internal 32kHz oscillator. This oscillator is started-up at power on and is used to clock the charge pump for the LCD voltage generation. It can be used to derive the frame clock instead of an input via a device pin.
The AX2061 has 5 row terminals (COM0—COM4) and 76 segment terminals (SEG0—SEG75), so that it can drive an LCD display with a maximum of 380 (76 x 5) segments. The driving method is 1/1 duty to 1/5 duty dynamic drive with four voltages VSS, VD1, VD2 and VD3. lt is also possible to set static drive. LCD display on/off can be controlled by software.
The AX2061 can be programmed via a four wire serial interface according SPI using the pins CLK, MOSI, MISO and SEL. When the interface signal SEL is pulled low, a four byte command (T0-T3), followed by a variable length configuration data stream (T4-Tx) is expected on the input signal pin MOSI. Data read from the interface appears on MISO. Reading of most registers is possible but it is never necessary for the functionality of the AX2061. This means that it is optional to connect the MOSI pin to the mater microcontroller.
特性- Wide power supply range: from 2.2 V to 3.6 V
- Low power consumption
- 4-bit contrast register
- Selectable row drive configuration: static or 2/3/4/5 row multiplexing
- 76 x 5-bit RAM for display data storage
- Internal 32 kHz oscillator
- Auto-incremented display data loading
| 优势- Suitable for multiple applications
- Perfect choice for energy efficient designs
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数据表 (1)
产品订购型号
产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价) |
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AX2061-1-WD1 | Active | Pb-free
Halide free | | 联系BDTIC | NA | WJAR | 1 | 联系BDTIC |
订购产品技术参数
Product | Segments | Key Detection | VDD Min (V) | VDD Max (V) | VLCD Min (V) | VLCD Max (V) | VI for Interface (V) | Operating Temperature (°C) | Output Ports | PWM Outputs | Character Generator | Reset | Contrast Adjustment | Control Command |
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AX2061-1-WD1 | 1/1 to 1/5 Duty: 380 (76x5) | | 2.2 | 3.6 | | | | -40 to 85 | | | | | | |