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AX8052F100: Ultra-Low Power Microcontroller for RF Applications

The AX8052F100 is an ultra-low power microcontroller. It is optimized for use in battery powered applications together with RF ICs. The AX8052F100 offers high integration with attractive peripheral blocks, small footprint, easy communication with RF ICs, flexibility and ultra-low power consumption. The AX8052F100 microcontroller core executes the industry standard 8052 instruction set. The system clock can be programmed freely from DC to 20 MHz. As instructions are executed in a single cycle, the core can deliver 20 MIPS. A 64 kByte flash memory is provided, allowing to program applications in C. A fully associative cache and a pre-fetch controller hide the latency of the flash memory. AX8052F100 specifically targets ultra-low power applications. Four system clock sources can be selected on the fly, allowing to flexibly adapt the system speed to varying application needs. The core consumes 150 µA/MHz and AX8052F100 consumes 800 nA in sleep mode with wake-up timer running. The AX8052F100 features a dual channel DMA engine that can transfer data to and from XRAM to any peripheral on chip. A dedicated AES engine with own DMA engine is provided for encryption. Further peripherals include three general purpose timers with optional sigma-delta or PWM output mode. The timers can be used as baud rate generators for the two UARTs. A master/slave SPI interface is provided. A 10-bit, 500 kSample/s ADC with flexible input modes, as well as comparators allow to interface with analog data streams. The AX8052F100 has a specialized SPI master interface that can be used as an interface to radio ICs. It maps the radio chip registers directly into the X-bus address space.

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