The CAV25512H is a 512-Kb Serial CMOS EEPROM device internally organized as 64Kx8 bits. This features a 128-byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAV25512H device. The device features software and hardware write protection, including partial as well as full array protection.On-Chip ECC (Error Correction Code) makes the device suitable for high reliability applications.
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| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| 512-Kb SPI Serial CMOS EEPROM | CAV25512H/D (94kB) | 0 | Jul, 2016 |
| Document Title | Document ID/Size | Revision |
|---|---|---|
| UDFN8, 3x2, 0.5P | 517BU (56.6kB) | O |
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| CAV25512HU5E-GT3 | Active | AEC Qualified PPAP Capable Pb-free Halide free | UDFN-8 | 517BU | 1 | Tape and Reel | 3000 | $1.6933 |
| Product | Type | Density | Organization | Data Transmission Standard | fcycle Max (kHz) | tACC Max ns | VCC Min (V) | VCC Max (V) | Istandby Max (µA) | Iact Max (mA) | T Min (°C) | T Max (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CAV25512HU5E-GT3 | Serial | 512 kb | 64k x 8 | SPI | 10000 | 40 | 2.5 | 5.5 | 5 | 3 | -40 | 125 |
