MC100ELT20: Translator, TTL to Differential PECL _ BDTIC 中国领先电子元器件代理商

MC100ELT20: Translator, TTL to Differential PECL

The MC10ELT/100ELT20 is a TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of the ELT20 makes it ideal for those applications where space, performance and low power are at a premium. The 100 Series contains temperature compensation.

特性

1.5ns Typical Propagation Delay
PNP TTL Inputs for Minimal Loading
Flow Through Pinouts
ESD Protection: >4 KV HBM, >200 V MM
Operating Range: VCC= 4.75 V to 5.25 V with GND= 0 V
No Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 51 devices

应用注释 (17)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit	AN1596/D (189.0kB)	2
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
Translator, TTL to Differential PECL	MC10ELT20/D (77kB)	7

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for MC100ELT20D	MC100ELT20D.IBS (7.0kB)	2

封装图纸 (2)

Document Title	Document ID/Size	Revision
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100ELT20DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	联系BDTIC
MC100ELT20DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	联系BDTIC
MC100ELT20DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
MC100ELT20DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	联系BDTIC