MC100EP131: Quad D Flip-Flop with Set, Reset, and Differential Clock

The MC10EP131 is a Quad Master-slaved D flip-flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring the fastest AC performance available.Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and (CCbar) HIGH, then using the Clock Enable inputs for clocking (C0-3 and C0-3bar).Common clocking is achieved by holding the C0-3 inputs LOW and C0-3bar inputs HIGH while using the differential common clock CC to clock all four flip-flops. When left floating open, any differential input will disable operation due to input pulldown resistors forcing an output default state.Individual asynchronous resets (R0-3) and an asynchronous set (SET) are provided.Data enters the master when both CC and C0-3 are LOW, and transfers to the slave when either CC or C0-3 (or both) go HIGH.The 100 Series contains temperature compensation.

特性

460ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
Differential Individual and Common Clocks
Individual Asynchronous Resets
Asynchronous Set
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at VEE
Pb-Free Packages are Available

应用

High Performance Logic for test systems

封装

应用注释 (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock	MC10EP131/D (164.0kB)	10

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for MC100EP131FA VCC at 3.3 V	MC100EP131FA_33.IBS (6.0kB)	3

封装图纸 (1)

Document Title	Document ID/Size	Revision
QFN32, 5x5, 0.5P, 3.1x3.1EP	488AM (57.4kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EP131FAG	Active	Pb-free Halide free	LQFP-32	联系BDTIC	2	Tray JEDEC	250	联系BDTIC
MC100EP131FAR2G	Active	Pb-free Halide free	LQFP-32	联系BDTIC	2	Tape and Reel	2000	联系BDTIC
MC100EP131MNG	Active	Pb-free Halide free	QFN-32	488AM	1	Tube	74	联系BDTIC
MC100EP131MNR4G	Lifetime	Pb-free Halide free	QFN-32	488AM	1	Tape and Reel	1000

订购产品技术参数

Product	Type	Bits	Input Level	Output Level	VCC Typ (V)	tJitter Typ (ps)	tpd Typ (ns)	tsu Min (ns)	th Min (ns)	trec Typ (ns)	tR & tF Max (ps)	fToggle Typ (MHz)
MC100EP131FAG	D-Type	4	CML ECL	ECL	5 3.3	0.2	0.46	0.12	0.12	0.21	250	3000
MC100EP131FAR2G	D-Type	4	ECL CML	ECL	3.3 5	0.2	0.46	0.12	0.12	0.21	250	3000
MC100EP131MNG	D-Type	4	CML ECL	ECL	3.3 5	0.2	0.46	0.12	0.12	0.21	250	3000