MC100EP40: Phase-Frequency Detector, 3.3 V / 5 V, ECL Differential

The MC100EP40 is a three-state phase-frequency detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V / 5 V power supply. When Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO. When Reference (R) and Feedback (FB) inputs are 80 pS or less in phase difference, the Phase Lock Detect pin will indicate lock by a high state. The VTX (VTR, VTRbar , VTFB , VTFBbar ) pins offer an internal termination network for 50 line impedance environment shown in Figure 2. An external sinking supply of VCC-2 V is required on VTX pin(s). If you short the two differential VTR and VTR (or VTFB and VTFBbar ) together, you provide a 100 termination resistance that is compatible with LVDS signal receiver termination. For more information on termination of logic devices, see AND8020. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinkingto 0.5 mA. When not used, VBB should be left open. For more information on Phase Lock Loop operation, refer to AND8040. Special considerations are required for differential inputs under No Signal conditio

特性
  • Maximum Frequency > 2 Ghz Typical
  • Fully Differential
  • Advanced High Band Output Swing of 400 mV
  • Theoretical Gain = 1.11
  • Trise 97 pS Typical, Ffall 70 pS Typical
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • 50Ω Internal Termination Resistor
  • These are Pb-Free Devices
封装
应用注释 (13)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Phase-Frequency Detector, 3.3 V / 5 V, ECL DifferentialMC100EP40/D (84kB)13Apr, 2014
仿真模型 (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for mc100ep40dt for 3.3VMC100EP40DT_33V.IBS (8.0kB)1
封装图纸 (1)
Document TitleDocument ID/SizeRevision
TSSOP-20 WB948E-02 (39.7kB)D
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC100EP40DTGActivePb-free Halide freeTSSOP-20948E-021Tube75联系BDTIC
MC100EP40DTR2GActivePb-free Halide freeTSSOP-20948E-021Tape and Reel2500联系BDTIC
订购产品技术参数
ProductInput LevelOutput LevelVCC Typ (V)Transfer Gain Typ (mV/degree)CMRR Max (V)fToggle Max (MHz)tpd Typ (ns)tJitter Typ (ps)tR & tF Max (ps)
MC100EP40DTGCML ECLECL5 3.30.93220000.550.2150
MC100EP40DTR2GCML ECLECL5 3.30.93220000.550.2150
Phase-Frequency Detector, 3.3 V / 5 V, ECL Differential (84kB) MC100EP40
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for mc100ep40dt for 3.3V MC100EP40
TSSOP-20 WB NLSX3018