MC100EP446: Serial to Parallel Converter, 3.3 V / 5 V, 8-Bit, CMOS / ECL / TTL Data Input

The MC10/100EP446 is an integrated 8-bit parallel to serial data converter. The device is designed with unique circuit topology to operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence from parallel data into a serial data stream is from bit D0 to D7. The parallel input pins D0-D7 are configurable to be threshold controlled by CMOS, ECL, or TTL level signals. The serial data rate output can be selected at internal clock data rate or twice the internal data rate using the CKSEL pin. Control pins are provided to reset (SYNC) and disable internal clock circuitry (CKEN). In either CKSEL modes, the internal flip-flops are triggered on the rising edge for CLK and the multiplexers are switched on the falling edge of CLK, therefore, all associated specification limits are referenced to the negative edge of the clock input. Additionally, VBB pin is provided for single-ended input condition. The 100 Series devices contain temperature compensation network.

特性

3.2 Gb/s Typical Data Rate Capability
Differential Clock and Serial Inputs
VBB Output for Single-ended Input Applications
Asynchronous Data Reset (SYNC)
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Parallel Interface Can Support PECL, TTL and CMOS
Pb-Free Packages are Available

应用

Parallel to Serial Conversion

封装

应用注释 (13)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
Serial / Parallel Converter, 3.3 V / 5 V, 8-Bit, CMOS / ECL / TTL Data Input	MC10EP446/D (185kB)	11

仿真模型 (2)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for MC100EP446FA -3.3 V	MC100EP446FA_-33.IBS (6.0kB)	2
IBIS Model for mc100ep446fa 3.3V	MC100EP446FA_33.IBS (6.0kB)	1

封装图纸 (1)

Document Title	Document ID/Size	Revision
QFN32, 5x5, 0.5P, 3.1x3.1EP	488AM (57.4kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EP446FAG	Active	Pb-free Halide free	LQFP-32	联系BDTIC	2	Tray JEDEC	250	联系BDTIC
MC100EP446FAR2G	Lifetime	Pb-free Halide free	LQFP-32	联系BDTIC	2	Tape and Reel	2000
MC100EP446MNG	Active	Pb-free Halide free	QFN-32	488AM	1	Tube	74	联系BDTIC
MC100EP446MNR4G	Lifetime	Pb-free Halide free	QFN-32	488AM	1	Tape and Reel	1000