MC100EP51: ECL D Flip-Flop with Reset and Differential Clock _ BDTIC 中国领先电子元器件代理商

MC100EP51: ECL D Flip-Flop with Reset and Differential Clock

The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLKbar input will be biased at VCC / 2.

特性

350ps Typical Propagation Delay
Maximum Frequency > 3 Ghz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Pb-Free Packages are Available

应用

封装

应用注释 (17)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit	AN1503/D (120.0kB)	6
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
D Flip Flop with Set and Reset	MC10EP51/D (150.0kB)	10

仿真模型 (2)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for MC100EP51D 3.3V	MC100EP51D_33.IBS (5.0kB)	1
IBIS Model for MC100EP51DT 3.3V	MC100EP51DT_33.IBS (5.0kB)	1

封装图纸 (3)

Document Title	Document ID/Size	Revision
DFN8 2.0x2.0x0.9mm, 0.5p	506AA (31.8kB)	F
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EP51DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	联系BDTIC
MC100EP51DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	联系BDTIC
MC100EP51DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
MC100EP51DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	联系BDTIC
MC100EP51MNR4G	Active	Pb-free Halide free	DFN-8	506AA	1	Tape and Reel	1000	联系BDTIC

订购产品技术参数

Product	Type	Bits	Input Level	Output Level	VCC Typ (V)	tJitter Typ (ps)	tpd Typ (ns)	tsu Min (ns)	th Min (ns)	trec Typ (ns)	tR & tF Max (ps)	fToggle Typ (MHz)
MC100EP51DG	D-Type	1	CML ECL	ECL	3.3 5	0.2	0.32	0.1	0.1	0.15	170	3000
MC100EP51DR2G	D-Type	1	CML ECL	ECL	3.3 5	0.2	0.32	0.1	0.1	0.15	170	3000
MC100EP51DTG	D-Type	1	ECL CML	ECL	3.3 5	0.2	0.32	0.1	0.1	0.15	170	3000
MC100EP51DTR2G	D-Type	1	ECL CML	ECL	5 3.3	0.2	0.32	0.1	0.1	0.15	170	3000
MC100EP51MNR4G	D-Type	1	CML ECL	ECL	3.3 5	0.2	0.32	0.1	0.1	0.15	170	3000